The present invention relates generally to a method of layout processing including layout data verification for integrated circuits.
For design of integrated circuits, generally effected is a layout data processing such as format transformation, OR processing and AND processing. Also included in the layout data processing is a data verification processing such as a design rule check (see Neil Weste, Kawran Eshraghian, "Principles of CMOS VLSI Design", ADDISON-WESLEY PUBLISHING COMPANY pp. 99-102, pp. 258) and an electrical rule check which is employed generally for integrated circuits each comprising a plurality of circuit blocks and inter-block routings (or wiring). One known approach is to perform at once the data verification for the entire layout data of an integrated circuit which consists of all block layout data and inter-block routing layout data. One problem with such a data verification processing is, however, that in application to highly integrated circuits the required memory capacity becomes extremely large. One possible solution is to individually verify the block layout data and the inter-block routing layout data. However, such an approach makes it difficult to perform data verification for boundary portions between the blocks and the inter-block routings.